1. Field of the Invention
The present invention relates to a delay calculation method for calculating delay time of, for example, each macrocell with transistors.
2. Description of the Background Art
For timing verification of semiconductor integrated circuits (SOC: System on Chip) equipped with large-scale systems, delay time in each instance must be calculated with accuracy. One of well-known high-precision delay calculation methods is that using circuit simulations such as SPICE. In circuit simulations, the analysis of operating points of each device is made on matrix calculation. This calculation is conducted at each lapse of a very short time to obtain a voltage value at every node. In this technique, a huge matrix must be analyzed for the analysis of operation at a certain time, so an increase in the number of devices will markedly increase the amount of calculation. Further, the necessity of conducting matrix calculation at each lapse of a very short time makes impossible to conduct an analysis within a realistic time, for semiconductor integrated circuits which include an extremely large number of devices such as large-scale SOCs. To solve this problem, another delay calculation method using a delay calculator has been employed.
The delay calculator previously adds an input waveform generating circuit and an output load respectively to the input and output of every macrocell (logic circuit) that can cause a delay, and it conduct circuit simulations (SPICE) using a plurality of kinds (usually 10 to 100) of input waveforms and output load capacitances. At this time, every input waveform is replaced and represented as time (a Tslew value) required for transition from low to high state (or high to low state).
From simulation results obtained here, parameters which are necessary for calculating delay time as a function of the Tslew value and the output load capacitance are extracted and stored in a delay-parameter database. This is done for each path when each macrocell has a plurality of different changing paths.
Using the delay-parameter database created in this way, the delay calculator performs delay calculations on a SOC. First, delay time in the instance where the Tslew value is set by default or by the designer is calculated using the delay-parameter database. For delay calculation, information on the output load is necessary, and it can be produced in advance from layout results obtained with a layout extractor. By so doing, delay time and an output waveform in that instance can be determined. Since the Tslew value to be inputted in the following instance can be determined from the output waveform, the delay time and the output waveform for the following instance can be determined using this Tslew value. This operation is performed for all instances, whereby any delay time in the SOC can be calculated.
For example, Japanese Patent Application Laid-open No. 2002-123568 has disclosed one of the delay calculation methods for calculating delay time only from Tslew values and output load information.
However, in real SOCs, depending on the topology of a circuit or RC network to be configured, there are various shapes of input waveforms that differ from the one used to create the delay-parameter database. That is, there exist a lot of input waveforms that have the same Tslew value but have different waveform shapes.
In conventional delay calculation methods, delay time is calculated only from Tslew values and output load information. Thus, in the case where the output load capacitance is the same and each input waveform has the same Tslew value, the same delay time is calculated for different shapes of input waveforms.
Consequently, the results of delay calculations in conventional delay calculation methods have a margin of error of around 8 percent even if parameters are optimized somehow. At present, SOCs become faster, so a margin of error in delay calculation must be kept at 5 percent at most. From this, the 8-percent inherent margin of error has made circuit design difficult.